1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capturing data in response to a data strobe signal.
2. Description of the Background Art
A progress for a high information transmitting rate in information industry in recent years is also requested in the domain of a dynamic random access memory (hereinafter referred to as DRAM.
In such circumstances, in order to achieve supply and reception of data at a high rate, a double data rate synchronous dynamic random access memory (DDR SDRAM) has been adopted. DDR SDRAM can input/output data at a data rate twice that of a clock signal in synchronism with leading and trailing edges of a clock signal. In DDR SDRAM, an internal operation thereof is controlled with a clock signal. In a case where data is captured, the data is captured using a data strobe signal DQS inputted externally.
As a result, DDR SDRAM has a requirement to synchronize the data captured in synchronism with data strobe signal DQS, further, with a clock signal.
FIG. 25 is a block diagram showing a configuration of a data processing system using DDR SDRAM.
Referring to FIG. 25, the data processing system 1 includes a controller 2 and plural DIMMs 3 each constituted of DDR SDRAM.
Controller 2 controls all of processing system 1. Controller 2 outputs clock signal CLK for controlling each of DIMMs 3. Furthermore, controller 2 outputs data strobe signal DQS that is used when each DDIM 3 captures data.
While clock signal buses 4 are provided to respective DIMMs 3, a data strobe signal bus 5 is provided as a common bus with DIMMs 3.
As a result, a phase difference arises between clock signal CLK inputted to each DIMM and data strobe signal DQS. That is, while clock signal CLK inputted to each DIMM and clock signal have the same input timing as each other, a phase shift occurs on the side of data strobe signal DQS inputted to each DIMM. To DIMM3 closest to controller 2, data strobe signal DQS is inputted in timing earlier than clock signal CLK, while to DIMM3 farthest from controller 2, data strobe signal is inputted in timing later than clock signal CLK.
Further detailed description will be given of such a shift in phase.
FIG. 26 is a block diagram showing a configuration of a data input circuit in DDR SDRAM.
Referring to FIG. 26, a data input circuit 10 includes: a data strobe signal DQS synchronization circuit 12 and a clock signal CLK synchronization circuit.
Data strobe signal DQS synchronization circuit 12 includes latch circuits L1 to L5 transmission gates TM1 to TM4 and an inverter IV21.
Latch circuits L1 to L5 receive data strobe signal DQS at the clock terminals. Latch circuit L1 receives an internal data signal DQ at the input terminal when data strobe signal DQS is at L level. Furthermore, latch circuit L1 latches internal data signal DQ having received at the input terminal thereof to output a signal xcfx86A0 when data strobe signal DQS is at H level.
Latch circuit L2 receives signal xcfx86A0 when data strobe signal DQS is at H level. Furthermore, latch circuit L2 latches signal xcfx86A0 to output a signal xcfx86A1 when data strobe signal DQS is at L level.
Latch circuit L4 receives internal data signal DQ when data strobe signal DQS is at H level. Furthermore, latch circuit L4 latches internal data signal DQ having received at the input terminal thereof to output a signal xcfx86B1 when data strobe signal DQS is at L level.
Transmission gates TM1 to TM4 are each constituted of a P channel MOS transistor and an N channel MOS transistor.
Transmission gate TM1 is connected between latch circuit L2 and latch circuit L3. An output signal of inverter IV21 is inputted to the gate of the P channel MOS transistor in transmission gate TM1. Furthermore, an address signal ADD externally inputted is inputted to the gate of the N channel MOS transistor in transmission gate TM1.
Transmission gate TM2 is connected between latch circuit L2 and latch circuit L5. The output signal of inverter IV21 is inputted to the gate of the N channel MOS transistor in transmission gate TM2. Furthermore, address signal ADD is inputted to the gate of the P channel MOS transistor in transmission gate TM2.
Transmission gate TM3 is connected between latch circuit L4 and latch circuit L3. The output signal of inverter IV21 is inputted to the gate of the N channel MOS transistor in transmission gate TM3. Furthermore, address signal ADD is inputted to the gate of the P channel MOS transistor in transmission gate TM3.
Transmission gate TM4 is connected between latch circuit L4 and latch circuit L5. The output signal of inverter IV21 is inputted to the gate of the P channel MOS transistor in transmission gate TM4. Furthermore, address signal ADD is inputted to the gate of the N channel MOS transistor in transmission gate TM4.
Note that inverter IV21 receives address signal ADD to invert the signal and to output the inverted signal. When address signal ADD is at H level, transmission gates TM1 and TM4 are turned on while transmission gates TM2 and TM3 are turned off. Accordingly, signal xcfx86A1 outputted from latch circuit L2 is inputted to latch circuit L3. Furthermore, signal xcfx86B1 outputted from latch circuit L4 is inputted to latch circuit L5.
When address signal ADD is at L level, transmission gates TM2 and TM3 are turned on while transmission gates TM1 and TM4 are turned off. Accordingly, signal xcfx86A1 outputted from latch circuit L2 is inputted to latch circuit L5. Furthermore, signal xcfx86B1 outputted from latch circuit L4 is inputted to latch circuit L3.
As a result, address signal ADD changes a transmission path of internal data signal DQ.
Latch circuit L3 receives a signal at the input terminal when data strobe signal DQS is at L level. Furthermore, latch circuit L3 latches the signal having received at the input terminal to output a signal xcfx86A2 when data strobe signal DQS is at H level.
Latch circuit L5 receives a signal at the input terminal when data strobe signal DQS is at L level and latches the signal having received at the input terminal to output a signal xcfx86B2 when data strobe signal DQS is at H level.
Clock signal synchronization circuit 13 includes latch circuits L6, L7, L22 and L23. Latch circuit L6 receives signal xcfx86A2 when clock signal CLK is at L level and latches signal xcfx86A2 and output the signal to latch circuit L22 when clock signal CLK is at H level. Latch circuit L22 receives an output signal of latch circuit L6 when clock signal CLK is at H level and latches an output signal of latch circuit L6 to output the signal as a signal xcfx86A4 to a circuit in DDR SDRAM when clock signal CLK is at L level.
Latch circuits L7 and L23 operate in a similar way to the cases of latch circuits L6 and L22. Latch circuit L7 receives signal xcfx86B2 at the input terminal thereof and latch circuit L23 outputs signal xcfx86B4 to a circuit in DDR SDRAM.
FIG. 27 is a timing chart showing operation of data input circuit 10 of FIG. 26.
Referring to FIG. 27, in DDR SDRAM, data DQ is in synchronism with rising edge and falling edges of data strobe signal DQS. A data signal DQ1 is in synchronism with the rising edge of data strobe signal DQS. Data signal DQ1 includes a set-up time tDS and a hold time DH relative to data strobe signal DQS. A data signal DQ2 is in synchronism with the falling edge of data strobe signal DQS. Data signal DQ2 includes a set-up time tDS and a hold time DH relative to data strobe signal DQS similar to data DQ1.
Now, on the assumption that address signal ADD is at H level, description will be given of operation in data input circuit 10.
First of all, description will be given of operation in latch circuit L1 in data input circuit 10.
Just before time t1, data strobe signal DQS is at L level. Therefore, latch circuit L1 receives data DQ1. At time t1, since data strobe signal DQS rises to H level, signal xcfx86A0 outputted from latch circuit L1 becomes data signal DQ1. Even at time t2 since data strobe signal DQ stays at H level, signal xcfx86A0 keeps on being data signal DQ1 as it is. At time t3, data strobe signal DQS falls to L level. Hence, at this time, latch circuit L1 receives data signal DQ2. Therefore, signal xcfx86A0 keeps on being data DQ2 during hold time DH of data DQ2 from time t3.
Then, description will be given of operation in latch circuit L2.
At time t1, data strobe signal DQS rises to H level. Hence, circuit L2 receives signal xcfx86A0. At time t3, data strobe signal DQS falls, but signal xcfx86A0 keeps on being data DQ1 till time t3, so signal xcfx86A1 outputted from latch circuit L2 is latched at data DQ1. Therefore, signal xcfx86A1 is kept on being fixed at DQ1 till time t4.
Latch circuit L3 receives signal xcfx86A1 when data strobe signal DQL is at L level and latches signal xcfx86A1 to output signal xcfx86A2 when data strobe signal DQS is at L level. Hence, signal xcfx86A2 outputted from latch circuit L3 keeps on being data signal DQ1 in a period from time t3 to t5.
Since latch circuit L4 receives an input signal from the input terminal thereof when data strobe signal DQS is at H level, latch circuit L4 receives data DQ1 at time t1. When at time t2, data signal changes from DQ1 to DQ2, and then latch circuit L4 receives data signal DQ2 instead. As a result, signal xcfx86B1 outputted from latch circuit 14 is data signal DQ1 in a period from time t1 to t2 and data signal DQ2 in a period from time t2 to t4.
Latch circuit L5 receives a signal when data strobe signal DQS is at L level. As a result, signal xcfx86B2 outputted from latch circuit L5 is data DQ2 in a period from time t3 to t5.
As a result of the above operation, data DQ1 and DQ2 inputted as a serial signal externally is separated in data strobe signal DQS synchronization circuit 12 and a data length becomes to be of one cycle.
Then, description will be given of operation in clock signal CLK synchronization circuit 13.
Latch circuit L6 latches signal xcfx86A2 when clock signal at L level. Hence, signal xcfx86A3 outputted from latch circuit L6 keeps on being data DQ1 in a period from time t3 to t5. Likewise, signal xcfx86B3 outputted from latch circuit L7 keeps on being data DQ2 in a period from time t3 to t5.
With the above operation applied, data DQ1 and DQ2 inputted in synchronism with data strobe signal DQS is synchronized with clock signal CLK. Data DQ1 and DQ2 having synchronized with clock signal CLK is outputted to circuits in DDR SDRAM.
The maximum operating frequency of a prior art DDR SDRAM was of the order of 100 MHz. In addition, a variation in phase of data strobe signal DQS relative to clock signal CLK was restricted within xc2x10.25 cycle.
FIG. 28 is a timing chart showing operation of data input circuit 10 in a case where a phase difference between clock signal CLK and data strobe signal DQS is produced.
Referring to FIG. 28, a data strobe signal DQS1 is data strobe signal DQS in a case where it suffers a phase difference of xe2x88x920.25 cycle relative to clock signal CLK (hereinafter referred to as xe2x88x920.25 tCLK). Hereinafter, this state is described such that data strobe signal DQS earlier than clock signal CLK.
A signal xcfx86A2-1 is a signal outputted from latch circuit L3 in a case of data strobe signal DQS1.
A data strobe signal DQS2 is data strobe signal DQS in a case where it suffers no phase difference relative to clock signal CLK. A signal xcfx86A2-2 is a signal outputted from latch circuit L3 in a case of data strobe signal DQS2. A data strobe signal DQS3 is data strobe signal DQS in a case where it produces a phase difference of +0.25 tCLK relative to clock signal CLK. Hereinafter, this state is described such that data strobe signal DQS later than clock signal CLK.
A signal xcfx86A2-3 is a signal outputted from latch circuit L3 in a case of a data strobe signal DQS3.
In the case of FIG. 28, data strobe signal DQS is restricted within xc2x10.25 tCLK. Therefore, a data length (1 tCLK) of each of signals xcfx86A2 to xcfx86A3 is longer than total time of variation 0.5 tCLK and set-up time tDS and hold time tDH.
Hence, clock signal CLK synchronization circuit 13 can capture normal data at all times.
However, in a case where an operation speed of DDR SDRAM is further faster, that is an operating frequency thereof is further higher, according to a request for increase in operation speed in recent years, data transfer is disabled from data strobe signal DQS synchronization circuit to clock signal CLK synchronization circuit.
FIG. 29 is a timing chart showing operation in data input circuit 10 in a case where a phase difference is produced between clock signal CLK and data strobe signal DQS at an operating frequency twice that in FIG. 28.
Referring to FIG. 29, data strobe signals DQS1 to DQS3 and signals xcfx86A2-1 to xcfx86A2-3 are the same as in FIG. 28; therefore, no description thereof is repeated.
A variation of data strobe signal DQS relative to clock signal CLK is not dependent on an operating frequency. Therefore, a variation is xc2x10.25 tCLK at an operating frequency of 100 MHz, while a variation is xc2x10.5 tCLK at an operating frequency of 200 MHz.
Accordingly, a data length (1 tCLK) of each of signals xcfx86A2-1 to xcfx86A2-3 is much shorter than total time of variation 1.0 tCLK and set-up time tDS and hold time tDH.
As a result, clock signal CLK synchronization circuit 13 cannot capture normal data.
In such a way, when an operating frequency increases, a possibility of causing DDR SDRAM to malfunction is higher unless it is grasped what level a phase difference is produced between data strobe signal DQS and clock signal CLK at and a proper measure is taken against the phase difference.
It is an object of the present invention to provide a semiconductor memory device capable of correctly grasping a phase difference between data strobe signal DQS and clock signal CLK to perform normal operation even at a high operation speed.
A semiconductor memory device according to the present invention includes: a detection circuit detecting a phase difference between a clock signal inputted externally and a strobe signal, which is inputted externally, and which is a signal for capturing data, to output a result of the detection as a detection signal; and a data input circuit inputting the data in response to the detection signal.
Thereby, detection can be achieved of a phase difference between a data strobe signal and a clock signal, thereby enabling control on the data input circuit according to a detection result.
According to the present invention, a phase difference between a data strobe signal and a clock signal can be detected. Furthermore, by controlling circuits in a semiconductor memory device using a result of the detection, correct data can be externally captured.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.